Junior/Associate Design & Verification Engineer
Posted on 7 Apr 2026
Deadline on 1 May 2026
Description

Dynamic Solution Innovators (DSi) stands at the forefront of the semiconductor industry, not merely as a participant but as a catalyst for its evolution. Through strategic collaboration with leading semiconductor firms, DSi accelerates design cycles with a strong focus on VLSI Design & Verification. Our comprehensive design services span RTL Design, Logical and Physical Synthesis, Signoff Checks, Package Design, and Firmware Development—contributing to the integrated circuits that power modern technology.

At DSi, we foster a culture of innovation while emphasizing continuous skill development. Our environment supports engineers in expanding their expertise, taking ownership of complex verification challenges, and contributing meaningfully to high-impact projects.

As a Design Verification Engineer at DSi, you will play a critical role in validating complex digital designs. You will work closely with design and architecture teams, develop robust verification environments, and ensure functional correctness of cutting-edge semiconductor products. Your hands-on experience and problem-solving ability will directly contribute to delivering high-quality silicon.

Be part of a team driving innovation in the semiconductor industry. Join DSi and contribute to shaping the next generation of digital systems. Apply now.

Responsibilities
  • Develop and execute verification plans for RTL designs
  • Create and maintain testbenches using SystemVerilog/UVM
  • Write directed and constrained-random test cases
  • Debug RTL and simulation issues, identify root causes, and propose fixes
  • Perform functional and code coverage analysis and closure
  • Collaborate closely with design and architecture teams
  • Contribute to regression setup and automation
Requirements
  • Bachelor’s degree in Electrical/Electronic Engineering or related field
  • 1–3 years of experience in Design & Verification
  • Strong knowledge of Verilog/SystemVerilog
  • Hands-on experience with UVM or similar verification methodology
  • Understanding of Digital Design fundamentals and computer architecture
  • Protocol in-depth understanding (e.g. AXI4, APB, SPI, UART)
  • Experience with simulation tools (e.g., VCS, Questa, Xcelium)
  • Familiarity with scripting languages (Python/Shell/TCL) is a plus

Preferred Skills

  • Experience in RISC-V or processor verification
  • Knowledge of formal verification is a plus
  • Exposure to FPGA/Emulation platforms is an advantage
Benefits
  • Opportunity to work on cutting-edge semiconductor projects
  • Collaborative and learning-driven environment
  • Competitive salary
  • Healthcare Benefits
  • In-campus fully subsidized lunch, snacks
  • Company paid training, courses and certification